Structured light imaging systems are commonly used for three-dimensional (3D) imaging. A structured light imaging system has two main parts: an illumination source and a sensing device including an array of pixels. The illumination source projects one or more light patterns onto an object being imaged and the pixels within the sensing device detect light reflected by the object. The detected light is then processed by the sensing device to generate a representation of the object.
FIG. 1 illustrates a typical four transistor (4T) pixel 50 utilized in a pixel array of an sensing device, such as a complementary metal-oxide-semiconductor (CMOS) sensing device. The pixel 50 includes a photosensor 52 (e.g., a photodiode), a storage node N configured as a floating diffusion (FD) region, transfer transistor 54, reset transistor 56, charge conversion transistor 58 configured as a source follower transistor, and row select transistor 60. The photosensor 52 is connected to the storage node N by the transfer transistor 54 when the transfer transistor 54 is activated by a transfer control signal TX. The reset transistor 56 is connected between the storage node N and an array pixel supply voltage VAA. A reset control signal RESET is used to activate the reset transistor 56, which resets the storage node N to a known state.
The charge conversion transistor 58 has its gate connected to the storage node N and is connected between the array pixel supply voltage VAA and the row select transistor 60. The charge conversion transistor 58 converts the charge stored at the storage node N into an electrical output signal. The row select transistor 60 is controllable by a row select signal ROW for selectively outputting the output signal OUT from the charge conversion transistor 58. For each pixel 50, two output signals are conventionally generated, one being a reset signal Vrst generated after the storage node N is reset, the other being an image or photo signal Vsig generated after charges are transferred from the photosensor 52 to the storage node N.
FIG. 2 illustrates a sensing device 200 that includes an array 230 of pixels (such as the pixel 50 illustrated in FIG. 1) and a timing and control circuit 232. The timing and control circuit 232 provides timing and control signals for enabling the reading out of signals from pixels of the pixel array 230 in a manner commonly known to those skilled in the art. The pixel array 230 has dimensions of M rows by N columns of pixels, with the size of the pixel array 230 depending on its application.
Signals from the sensing device 200 are typically read out a row at a time using a column parallel readout architecture. The timing and control circuit 232 selects a particular row of pixels in the pixel array 230 by controlling the operation of a row addressing circuit 234 and row drivers 240. Signals stored in the selected row of pixels are provided to a readout circuit 242 in the manner described above. The signals are read twice from each of the columns and then read out sequentially or in parallel using a column addressing circuit 244. The pixel signals (Vrst, Vsig) corresponding to the reset pixel signal and image pixel signal are provided as outputs of the readout circuit 242, and are typically subtracted by a differential amplifier 260 in a correlated double sampling operation and the result digitized by an analog to digital converter 264 to provide a digital pixel signal. The digital pixel signals represent an image captured by pixel array 230. The digital pixel signals are processed in an image processing circuit 268 to produce an output image.